In many types of electrical systems it is desirable to generate clock signals with various frequency and phase relationships synthesized from certain reference signals. A common way to synthesize derivatives of a reference signal is based upon the analog phase locked loop (PLL) frequency converter. Accordingly, FIG. 1 shows a traditional analog PLL 100 that takes a digital source frequency SCLK as an input to a source divider 104 that divides SCLK by an integer value S to create reference frequency fREF. A negative feedback PLL control loop 105 is formed by a phase detector 106, a charge pump 108, a low pass filter 110, a voltage controlled oscillator (VCO) 112, and a feedback divider 114. Phase detector 106 performs a phase difference operation on fREF and feedback frequency fBACK. That is, phase detector 106 generates a phase error signal UERR that is zero when fREF and fBACK are equal, and varies inversely with their difference. The feed-forward part 107 of the PLL control loop generates an output, or destination, frequency DCLK from VCO 112 whose output frequency is controlled by UERR through a voltage created by charge pump 108 and low pass filter 110. Specifically, charge pump 108 converts UERR to a voltage signal that is smoothed by low pass loop filter 110, thereby providing a control voltage to VCO 112. The feedback path 113 of the PLL control loop feeds frequency output DCLK into feedback divider 114, which creates the fBACK signal by dividing DCLK by integer value F. The output frequency of DCLK is a multiple or fraction source frequency SCLK as determined by the ratio F/S.
PLL phase jitter, loop stability and response time are principally determined by analog charge pump 108 and low pass loop filter 110 components. Capacitive elements in these analog PLL components introduce significant loop time constants and phase jitter that result in loop behavior that is difficult to understand and predict, especially when the source frequency SCLK rapidly changes. One reason for this uncertainty, for example, is that capacitors are subject to thermal variation of their electrical characteristics. For at least these reasons, conventional analog PLLs are very difficult to practically use for accurate frequency conversion, especially when the source frequency SCLK is not a constant value. In addition to electrical performance limitations, there are significant costs associated with the implementation of conventional analog PLLs. For example, when implemented in an integrated circuit (IC), the analog PLL components take a significant portion of the final IC die area. Another significant cost associated with the analog PLL is that current IC device testing techniques require external IC access pins connected to the analog PLL for inspection by specialized testing equipment. In some cases, selection of dividers 114 and 104 can also present important cost and design problems. By way of example, if dividers with too few bits are used (e.g., 4) there would be a range of output frequencies that such a PLL could not produce due to the limited resolution of the dividers. However, it is often not practical to increase the number of bits in these dividers, as this can increases the compare period, resulting in larger and more costly capacitive elements in the analog PLL. Moreover, the problem of selecting a small divider ratio is made more difficult by the fact that many conventional clock sources are derived from crystal oscillators that come in relatively few discrete frequency values.
Instead of fixed-frequency crystal oscillators, some known methods implement a digital oscillator to generate DCLK. One conventional digitally controlled oscillator is called a discrete-time oscillator (DTO), and is shown by way of example in FIG. 2 as DTO 200. The DTO 200 includes an n-bit adder 202 that adds the n-bit increment value N (a scaling factor) to the previous output value of register 204, whereby the output value of register 204 is updated with the newly incremented value upon the next rising edge of a reference clock signal RCLK, thereby generating, over some number of RCLK cycles the n-bit staircase output represented by signal 206. The reference clock signal RCLK controls the duration of each step in the staircase output signal 206 by synchronizing when register 204 is updated with the next DTO output value determined by adder 202. After each period of the DTO output signal 206, a carry bit 208 is generated. Carry bit 208 represents the integer part of the DTO output frequency, and the staircase DTO output signal 206 contains information about the fractional part of each period. A counter unit (not shown) may accumulate the carries 208 generated over successive periods, thereby accumulating the integer part of the DTO's output for use by other system components. The DTO oscillation period is determined by the MODULO (i.e., the counting range 2n) of the DTO adder, the value of N, and the RCLK frequency FRCLK according to the following Equation (1):
                              F          DCLK                =                              SF            MODULO                    ×                      F            RCLK                                              (        1        )            where SF is an n-bit scaling factor (e.g. N) that linearly determines the output frequency of the DTO.
Typically, the RCLK frequency MODULO are fixed, and the desired DTO output frequency is dynamically controlled by the value of N. Typically, MODULO=2n, where n is number of DTO adder bits. In some embodiments the DTO output frequency is controlled by changing MODULO while holding N constant. It should be noted that DTO 200 can be used in frequency conversion by having a module (not shown) that analyzes the input frequency to convert, and calculates the appropriate value of N for the DTO to generate the desired DCLK output frequency. However, one problem that such DTO frequency converters have is that the rising-edge and falling-edge of the DCLK output signal may be substantially miss-aligned relative to ideal position because change in the DTO output is made at the rising edge of the reference clock, RCLK. As a result, the jitter of the DCLK signal edges may be up to one RCLK period, and the value of jitter may be significantly worse than that of the analog PLL. This is particularly important when even one instance of phase jitter in the DTO output frequency could not be tolerated.
One known way to reduce phase jitter in the DTO output frequency is to use a digital-to-analog converter (DAC) as illustrated by the exemplary block diagram 300 in FIG. 3. In the diagram, an n-bit value N sets the frequency of the n-bit DTO signal fDTO, which is fed into output module 307 for signal conditioning. Output module 307 generates an arbitrary waveform with the same period as FDTO by taking the output of DTO 304 as a memory address for lookup table (LUT) 308 which inputs the appropriate values from each corresponding LUT address location into digital-to-analog converter (DAC) 310, which thereby generates the desired waveform that is smoothed by low-pass filter 312. The LUT and filter are usually included to reduce harmonic frequency distortion in the DTO output signal by blocking the highest harmonic frequencies and permitting principally the main clock frequency to pass through, there by also reducing, but not eliminating, phase jitter. Schmitt trigger 314 converts the analog representation of FDTO into a digital frequency SCLK that is fed into PLL 316 for next step of frequency conversion. The analog PLL smoothes the SCLK jitter, and, additionally, allows a reduction of the fDTO range relative to the DCLK range, which is important for the design of low-pass filter 312.
Important areas where frequency converters are often used include computer CRT and LCD monitors with digital interfaces. In such applications, there is a multiplicity of different digital clock frequencies that are generated, or converted from relatively few precise clock references. Functions performed that drive the need for many different clock frequencies include image shrinks and interpolation, and the different scanning frequencies required to support changes in image pixel dimensions.
Although known frequency converters have generally worked well, as digital systems require an ever-increasing number of precise digital clock frequencies, there is a need for an improved digital frequency converter design that is efficient to manufacture and test. In particular, it would be desirable to have an all-digital frequency converter that does not have an analog PLL.